Semitronix Releases DFTEXP

As IC technology becomes more complex, defects and yield issues are more likely to arise during the manufacturing process. To meet the Defective Parts per Million (DPPM) standard, multiple tests are conducted to eliminate defective chips and help diagnose yield issues. Design for Test (DFT) is a technique that is widely adopted in the industry. It enhances the testability of chips by adding test circuits to chip designs. However, the industry faces the challenges of lowering testing costs, reducing the area occupied by test circuits, and achieving higher fault coverage rates. In addition, pinpointing the exact location of faults is another challenge.

To overcome these challenges, Semitronix has collaborated with its subsidiary company YiChip and released a total solution for DFT and yield diagnostics - DFTEXP. DFTEXP is a comprehensive EDA platform that is integrated with advanced DFT EDA tools, DFT design flow, and yield diagnostics and analysis flow. With this platform, users can address the challenges of diagnosing and testing SoC and large-scale chips, performing functional safety testing for automotive devices, and improving yield. DFTEXP can help customers improve product quality and reduce testing costs, contributing to the growth of the yield enhancement ecosystem.

Benefits

• DFTEXP covers a complete suite of DFT EDA tools and supports the implementation of DFT designs for chips across various fields, including MCU, AI, GPU, Network, 5G Baseband, and AP. It supports In-System-Test and functional safety testing for automotive devices.
   

• DFTEXP provides a comprehensive yield diagnostics and enhancement solution that can adapt to different processes and fab requirements. It helps locate root causes of yield issues and establish yield enhancement solutions through the DFT Diagnosis and DATAEXP system. By integrating DFT diagnostic results with chip-related data from DATAEXP-YMS, such as product layout, WAT, CP, and FT data, inline data, equipment, and defect data, DFTEXP allows for more accurate fault detection and yield issues root cause identification, accelerating the time-to-market cycle for chip products.
  
  
  

DFTEXP features an automated DFT implementation flow and a comprehensive wafer acceptance flow. It supports both RTL and Netlist Flow and accelerates the time-to-market cycle for products through hierarchical DGT and hierarchical ATPG flows. DFTEXP helps establish a comprehensive wafer acceptance flow to meet the DPPM requirements of various chip designs.

DFTEXP is highly synergistic with Semitronix’s existing yield enhancement system, DATAEXP-YMS, connecting the silicon lifecycle data chain from design to manufacturing and testing. DFTEXP helps fabless companies reduce costs and quickly locate root causes of yield issues. Meanwhile, DFTEXP provides fabs with a complete suite of DFT and yield diagnostics tools, helping to optimize manufacturing processes.

Semitronix will continue to invest efforts into the development of total solutions to meet the industry's growing challenges and contribute to the growth of the global semiconductor industry.